1. Field of the Invention
The method and apparatus of the present invention relates generally to the sensing of data in a memory, and more particularly to the sensing of data levels for read only memories.
2. Art Background
Read only memories (ROMs), whether implemented as stand alone memory circuits or used in a processor register file, typically include a number of memory locations arranged in a matrix of rows and columns. The contents of a memory location are read by applying an input voltage to a selected wordline, or row, and sensing whether the voltage of the bitline, or column, changes. The bitline acts as a capacitor, and is typically precharged to a predetermined voltage prior to reading the memory location. If the memory location includes a field effect transistor (FET) having its source coupled to ground, its drain coupled to the bitline, and its gate coupled to the selected wordline, the input voltage causes the FET to switch on, coupling the bitline to ground. Coupling the bitline to ground causes the bitline to discharge, and the voltage of the bitline drops towards ground, indicating a first logic state. If the memory location does not contain a FET, applying the input voltage has no effect on the bitline, and the bitline remains at the precharged voltage, indicating a second logic state.
Typical prior art ROMs use a sense amplifier to sense the state of the selected bitline. One type of sense amplifier is a single ended sense amplifier that has the bitline as its input. The presence of a transistor at the selected memory location is detected by the negative going voltage of the bitline, which is caused by the bitline discharging towards ground when the transistor is switched on.
One concern in sense amplifier design is the speed of the sense amplifier. The speed of the sense amplifier is determined by the sensitivity of the sense amplifier to the discharging of the bitline. A very sensitive sense amplifier has its trip-point voltage, V.sub.tp, very dose to the precharge voltage, which is typically VCC, such that a small drop in the voltage level of the bitline causes the sense amplifier to detect a programmed memory location. For a very low sensitivity sense amplifier, V.sub.tp may be ground. Of course, it typically takes more time to discharge the bitline from VCC to ground than it takes to discharge the bitline from VCC to VCC minus a millivolt. It also takes longer to precharge the bitline to VCC when the bitline is discharged to a lower voltage. Thus, the more sensitive the sense amp, the less time it will take to discharge and precharge the bitline.
Another consideration in sense amp design is power consumption. The act of charging and discharging the bitline results in power consumption. The greater the swing between precharged and discharged voltage levels, the greater the power consumption. This consideration is essential in portable computing devices. Therefore, the level to which the bitline must be precharged is important in portable computer designs.
A typical prior art solution is to provide a cascode device coupled between the bitline and the input of the output stage of the single-ended sense amplifier. The cascode device may be an n-channel field effect transistor having its drain coupled to the input of the output stage, its source coupled to fire bitline, and its gate coupled to a constant voltage source, typically VCC. A pull-up device is coupled to the drain such that the bitline is precharged to a voltage equal to the voltage of the constant voltage source minus the threshold voltage of the cascode transistor, at which time the cascode transistor switches off, decoupling the input of the output stage from the bitline. The input of the output stage will be precharged all the way to VCC. To reduce the precharge voltage swing, the constant voltage source may be some intermediate voltage between ground and VCC. During a read cycle, if the selected ROM location is programmed, the drop in the bitline voltage will cause the cascode transistor to switch on, coupling the bitline to the input of the output stage. The voltage at the input of the output stage drops rapidly to the voltage of the bitline through charge sharing. An example of such a circuit may be found in Design and Analysis of VLSI Circuits by Lance A. Glasser and Daniel W. Dobberpuhl, at pages 273-274.
A problem of this prior art sense amplifier is that noise on the bitline can cause the cascode transistor to inadvertently switch on, resulting in the reading of invalid data. This is due to the fact that the gate-source voltage of the device is just at the edge of the threshold voltage. Therefore, a noise margin must be provided to account for noise that can be injected on the bitline. Such noise can be, for example, a result of capacitive affects of adjacent bitlines in the matrix. Providing a sufficient noise margin increases the reliability of data.
As will be discussed, the method and apparatus of the present invention is directed to a dynamic single ended sense amplifier circuit having increased sense speed, decreased power consumption, and adjustable noise margins.